Power Button Override and Deep S4/S5 a. The following

Power Button Override and Deep S4/S5
a. The following note is added to the PWRBTN# Description in table 2-8 Power
Management Interface Signals:
Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and
conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5.
b. The following is added as note 5 to table 5-23 State Transition Rules for the PCH and
applies to all Power Button Override statements in the table:
Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and
conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5.
c. Table 5-32 Transitions Due to Power Button is modified as shown:
d. The Power Button Override Function sub-section of section 5.13.8.1 PWRBTN#
(Power Button) is replaced with the following:

If PWRBTN# is observed active for at least four consecutive seconds, the state machine
unconditionally transitions to the G2/S5 state or Deep S4/S5, regardless of present
state (S0–S4), even if the PCH PWROK is not active. In this case, the transition to the
G2/S5 state or Deep S4/S5 does not depend on any particular response from the
processor (such as, a DMI Messages), nor any similar dependency from any other
subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable using the
PWRBTN_LVL bit.
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition.

это оно? про s3# ничего не нашел 5 раз все пролистал. нашел только его бол аут ( D4 ) но это вряд ли поможет.