Из даташита на Ali1541/1542 Т.е. проще и надежнее

Supports Pipelined-Burst SRAM/Memory Cache
- Direct mapped, 256KB/512KB/1MB
- Write-Back/Dynamic-Write-Back cache policy
- Built-in 16K*2 bit SRAM for MESI protocol to
reduce cost and enhance performance
- Built-in 16K*10 bit SRAM for TAG data to reduce
cost and enhance performance (reserved)
- Cacheable memory up to 128MB with 8-bit Tag
SRAM when using 512KB L2 cache, 256MB when
using 256KB L2 cache.
- Cacheable memory up to 512MB with 10-bit Tag
SRAM when using 512KB L2 cache, 1GB when
using 256KB L2 cache
- 3-1-1-1-1-1-1-1 for Pipelined Burst SRAM/ Memory
Cache at back-to-back burst read and write cycles.
- Supports 3.3V/5V SRAMs for Tag Address.
- Supports CPU Single Read Cycle L2 Allocation.