== cut == SDATAINCLK # AMD Athlon System Bus

== cut ==
SDATAINCLK[3:0]#

AMD Athlon System Bus System Data In Clock
SDATAINCLK[3:0]# is the single-ended source-synchronous clock driven by the AMD-761
system controller to transfer data on SDATA[63:0]# and check bits on SCHECK[7:0]#.
Sixteen bits of data and two check bits are skew-aligned with each clock. Data is
transferred on each clock edge.
These signals are driven inactive (negated) when the CLKFWDRST signal is asserted (true).
When CLKFWDRST is negated, SDATAINCLK[3:0]# run continuously after three clock
delays.
== cut ==

еще бы какой дезигн гуид найти по этому поводу...