Вот из даташита на 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4). Чтобы програмили этот порт из _PTS, так невидно, но с другой стороны оно ж и неправильно работает... Так может этим сама ось занимается, но откуда она занает что к чему...
PMCNTRL—POWER MANAGEMENT CONTROL REGISTER (IO)
I/O Address: Base + (04h)
Default Value: 0000h
Attribute: Read/Write
Bit Description
15:14 Reserved.
13 Suspend Enable (SUS_EN)—R/W.
This is a write-only bit and reads to it always return a 0. Writing this bit to a 1 causes the system to automatically sequence into the suspend state defined by the SUS_TYP field. This bit corresponds to the SLP_EN bit in ACPI specification.
12:10 Suspend Type (SUS_TYP)—R/W.
Specifies the type of hardware suspend mode the system should enter when the SUS_EN bit is set. This field is decoded as follows:
Bits[12:10] Suspend Type
000 Soff/STD (Soft OFF or Suspend to Disk)
001 STR (Suspend To RAM)
010 POSCL (Powered On Suspend, Context Lost)
011 POSCCL (Powered On Suspend, CPU Context Lost)
100 POS (Powered On Suspend, Context Maintained)
101 Working (Clock Control)
110 Reserved
111 Reserved
The SUS_TYP field may also be used by the BIOS and OS code to determine the type of suspend state the system is resuming from. Before entering any low power clock control state (LVL2 or LVL3), this field should be programmed to the Working state (101). This does not cause any action by PIIX4, but is for information storage only.
9:3 Reserved.
2 Global Release (GBL_RLS)—R/W.
1=A 1 written to this bit position will cause an SMI# to be generated and BIOS_STS bit set if enabled by the BIOS_EN bit.
0=No SMI# generated. This bit is used by the ACPI software to raise an event to the BIOS software.
1 Bus Master Reload Enable (BRLD_EN_BM)—R/W.
1=Enable the generation of a Burst or Stop Break event upon setting of the BM_STS bit.
0=Disable.
0 SCI Enable (SCI_EN)—R/W.
1=Enable generation of SCI upon assertion of PWRBTN_STS, LID_STS, THRM_STS, or GPI_STS bits.
0=Disable.
Да уж, 1685 просмотров, и ниодного ответа, плохо
Я собственно почему спрашиваю
Вот из даташита на 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4). Чтобы програмили этот порт из _PTS, так невидно, но с другой стороны оно ж и неправильно работает... Так может этим сама ось занимается, но откуда она занает что к чему...
PMCNTRL—POWER MANAGEMENT CONTROL REGISTER (IO)
I/O Address: Base + (04h)
Default Value: 0000h
Attribute: Read/Write
Bit Description
15:14 Reserved.
13 Suspend Enable (SUS_EN)—R/W.
This is a write-only bit and reads to it always return a 0. Writing this bit to a 1 causes the system to automatically sequence into the suspend state defined by the SUS_TYP field. This bit corresponds to the SLP_EN bit in ACPI specification.
12:10 Suspend Type (SUS_TYP)—R/W.
Specifies the type of hardware suspend mode the system should enter when the SUS_EN bit is set. This field is decoded as follows:
Bits[12:10] Suspend Type
000 Soff/STD (Soft OFF or Suspend to Disk)
001 STR (Suspend To RAM)
010 POSCL (Powered On Suspend, Context Lost)
011 POSCCL (Powered On Suspend, CPU Context Lost)
100 POS (Powered On Suspend, Context Maintained)
101 Working (Clock Control)
110 Reserved
111 Reserved
The SUS_TYP field may also be used by the BIOS and OS code to determine the type of suspend state the system is resuming from. Before entering any low power clock control state (LVL2 or LVL3), this field should be programmed to the Working state (101). This does not cause any action by PIIX4, but is for information storage only.
9:3 Reserved.
2 Global Release (GBL_RLS)—R/W.
1=A 1 written to this bit position will cause an SMI# to be generated and BIOS_STS bit set if enabled by the BIOS_EN bit.
0=No SMI# generated. This bit is used by the ACPI software to raise an event to the BIOS software.
1 Bus Master Reload Enable (BRLD_EN_BM)—R/W.
1=Enable the generation of a Burst or Stop Break event upon setting of the BM_STS bit.
0=Disable.
0 SCI Enable (SCI_EN)—R/W.
1=Enable generation of SCI upon assertion of PWRBTN_STS, LID_STS, THRM_STS, or GPI_STS bits.
0=Disable.