Есть еще такая штука как "P6 Family of Processors. Hardware Developer’s Manual. September 1998"
И там существует следующая табличка (обратите внимание на названия сигналов):
Ну и соответствующий комментарий:
"The P6 family uses a ratio clock design, in which the bus clock is multiplied by a ratio to produce
the processor’s internal (or “core”) clock. The processor begins sampling LINT[1:0], A20M# and
IGNNE# on the inactive-to-active transition of RESET# to determine the core-frequency to busfrequency
relationship and immediately begins the internal PLL lock mode. On the active-toinactive
transition of RESET#, the processor internally latches the inputs to allow the pins to be
used for normal functionality. Effectively, these pins must meet a large setup time (please refer to
your processor datasheet for this value) to the active-to-inactive transition of RESET#."
Есть еще такая штука как "P6 Family of Processors. Hardware Developer’s Manual. September 1998"
И там существует следующая табличка (обратите внимание на названия сигналов):
Ну и соответствующий комментарий:
"The P6 family uses a ratio clock design, in which the bus clock is multiplied by a ratio to produce
the processor’s internal (or “core”) clock. The processor begins sampling LINT[1:0], A20M# and
IGNNE# on the inactive-to-active transition of RESET# to determine the core-frequency to busfrequency
relationship and immediately begins the internal PLL lock mode. On the active-toinactive
transition of RESET#, the processor internally latches the inputs to allow the pins to be
used for normal functionality. Effectively, these pins must meet a large setup time (please refer to
your processor datasheet for this value) to the active-to-inactive transition of RESET#."