PCI Bridge Features

The list of the main features of the PCI bridge IP core:
32-bit PCI interface
Fully PCI 2.2 compliant (with 66 MHz PCI specification)
Separated initiator and target functional blocks
Supported initiator commands and functions:
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
I/O Read, I/O Write
Configuration Read, Configuration Write
Bus Parking
Interrupt Acknowledge
Host Bridging
Supported target commands and functions:
Type 0 Configuration Space Header
(Type 0 is used to configure agents on the same bus segment)
(Type 1 is used to configure across PCI-to-PCI bridges)
Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
Memory Write and Invalidate (MWI)
I/O Read, I/O Write
Configuration Read, Configuration Write
Target Abort, Target Retry, Target Disconnect
Fast Back-to-Back Capable response
Full Command/Status registers
WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
Configurable on-chip FIFOs