"Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on
these pins is latched into their appropriate internal registers. Once the correct information is properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms.
Each of these pins has a large pull-up resistor (250 kΩ @3.3V) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if logic
0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor. Note that
this logic will only be latched at initial power on.
If optional EMI reducing capacitor is needed, they should be placed as close to the series terminating
resistor as possible and after the series-terminating resistor. These capacitors have typical values
ranging from 4.7pF to 22pF."
Это пояснение к схемам на стр.16 или 19, в зависимости от редакции даташита.
Поскольку в нашем случае, т.е. FSB-133, FSB/PCI-4 все выводы FSx должны быть logic 1, но этого не
происходит, то можно предположить, что производитель мат. платы сэкономит на рекомендуемых
резисторах 10 kΩ.
Возможно вся проблема только в FS3 (отсутствие резистора), т.к. на остальных FSx логический уровень
нормально переключается, а на FS3 "Zero forever" .
Выдержка из даташита на клокер:
"Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Fig1), therefore,
and are considered input select pins. When Vdd reaches 2.5V, the logic level that is present on
these pins is latched into their appropriate internal registers. Once the correct information is properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 ms) outputs starts to toggle at the specified frequency.
Within 3ms.
Each of these pins has a large pull-up resistor (250 kΩ @3.3V) inside. The default state will be logic
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 kΩ resistor is recommended to be
connected to Vdd if logic 1 is expected. Otherwise, there should be direct connection to ground if logic
0 is desired. The 10 kΩ resistor should be placed before the serious terminating resistor. Note that
this logic will only be latched at initial power on.
If optional EMI reducing capacitor is needed, they should be placed as close to the series terminating
resistor as possible and after the series-terminating resistor. These capacitors have typical values
ranging from 4.7pF to 22pF."
Это пояснение к схемам на стр.16 или 19, в зависимости от редакции даташита.
Поскольку в нашем случае, т.е. FSB-133, FSB/PCI-4 все выводы FSx должны быть logic 1, но этого не
происходит, то можно предположить, что производитель мат. платы сэкономит на рекомендуемых
резисторах 10 kΩ.
Возможно вся проблема только в FS3 (отсутствие резистора), т.к. на остальных FSx логический уровень
нормально переключается, а на FS3 "Zero forever" .
Несколько позже сей факт постараюсь проверить.