Встанет ли xeon E5310 s771 в socket 775?
Есть Quad Core Xeon DP E5310 1.60GHz 2x4MB 1066MHz за 100,00$
Для сравнения Q6600 (Socket 775 Core 2 Quad Q6600 2,40 GHz 8MB 1066MHz стоит > 6000 р.

Во-первых у них в разных местах находятся ключи - углубления в текстолите подложки:
Q6600 слева и справа внизу:
__________________ | | | +------+ | | | | | | +------+ | > < |________________/

то у Xeon 53xx сверху и снизу слева
_ _______________ | \/ | | +------+ | | | | | | +------+ | | | |_^______________/

Но положим - пропил, где надо, сделаем :)

Во-вторых беглое сравнение даташитов процессоров показало некие различия:
А именно:
# Land Name Q6600 # Land Name XEON различие A23 VCCA Power/Other A23 RESERVED * A24 FC23 Power/Other A24 RESERVED * A27 VTT Power/Other A27 КЛЮЧ * A28 VTT Power/Other A28 КЛЮЧ * A29 VTT Power/Other A29 КЛЮЧ * A30 VTT Power/Other A30 КЛЮЧ * AA2 FC39 Power/Other AA2 LL_ID1 Power/Other Output * AB3 FC37 Power/Other AB3 MCERR# Common Clk Input/Output * AD3 FC36 Power/Other AD3 BINIT# Common Clk Input/Output * AE3 FC18 Power/Other AE3 RESERVED * AF2 BPM4# Common Clk Input/Output AF2 BPM4# Common Clk Output * AH7 VSS Power/Other AH7 RESERVED * AJ1 BPM1# Common Clk Input/Output AJ1 BPM1# Common Clk Output * AJ3 ITP_CLK1 TAP Input AJ3 RESERVED * AJ7 VSS Power/Other AJ7 RESERVED * AK1 FC24 Power/Other AK1 RESERVED * AK3 ITP_CLK0 TAP Input AK3 RESERVED * AL1 FC25 Power/Other AL1 RESERVED * AL3 VRDSEL Power/Other AL3 VSS Power/Other * AM2 VID0 Power/Other Output AM2 RESERVED * AM6 FC40 Power/Other AM6 RESERVED * AN27 VSS Power/Other AN27 КЛЮЧ * AN28 VSS Power/Other AN28 КЛЮЧ * AN29 VCC Power/Other AN29 КЛЮЧ * AN4 VSS_SENSE Power/Other Output AN4 VSS_DIE_SENSE Power/Other Output * AN5 VCC_MB_ AN5 RESERVED * AN6 VSS_MB_ AN6 RESERVED * B13 COMP8 Power/Other Input B13 RESERVED * B23 VSSA Power/Other B23 RESERVED * C23 VCCIOPLL Power/Other C23 RESERVED * E1 КЛЮЧ E1 RESERVED Power/Other * E24 FC10 Power/Other E24 RESERVED * E29 FC26 Power/Other E29 RESERVED * E30 КЛЮЧ E30 VTT Power/Other * E5 FC20 Power/Other E5 RESERVED * F1 КЛЮЧ F1 VSS Power/Other * F30 КЛЮЧ F30 VTT Power/Other * F6 FC21 Power/Other F6 RESERVED * H15 FC32 Power/Other H15 DP1# Common Clk Input/Output * H16 FC33 Power/Other H16 DP2# Common Clk Input/Output * H29 FC15 Power/Other H29 VSS Power/Other * H4 FC35 Power/Other H4 RSP# Common Clk Input * H5 TESTHI10 Power/Other Input H5 BR1# Common Clk Input * J16 FC31 Power/Other J16 DP0# Common Clk Input/Output * J17 FC34 Power/Other J17 DP3# Common Clk Input/Output * J2 FC3 Power/Other J2 RESERVED * J3 FC22 Power/Other J3 RESERVED * K1 LINT0 ASync CMOS Input K1 LINT0 CMOS * L5 A03# Source Sync Input/Output L5 A05# Source Sync Input/Output * M5 A05# Source Sync Input/Output M5 A03# Source Sync Input/Output * N4 RESERVED N4 A36# Source Sync Input/Output * P1 TESTHI11 Power/Other Input P1 TESTHI10 Power/Other Input * P5 RESERVED P5 A37# Source Sync Input/Output * T2 FC4 Power/Other T2 RESERVED * U1 TDO_M TAP Output U1 TESTIN2 Power/Other Input * U2 FC29 Power/Other U2 AP0# Common Clk Input/Output * U3 FC30 Power/Other U3 AP1# Common Clk Input/Output * V2 RESERVED V2 LL_ID0 Power/Other Output * W2 TDI_M Power/Other Input W2 TESTIN1 Power/Other Input * Y1 FC0 Power/Other Y1 RESERVED * Y3 FC17 Power/Other Y3 RESERVED *

В-третьих:
В описании сигналов:
Q6600:
Name Type Description
A[35:3]# Input/Output
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See Section 6.1 for more details.
XEON:
A[37:3]# I/O
A[37:3]# (Address) define a 238-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In subphase 2, these signals transmit transaction type information. These signals must connect the appropriate pins of all agents on the FSB. A[37:3]#4 are protected by parity signals AP[1:0]#. A[37:3]#4 are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processors sample a subset of the A[37:3]#4 lands to determine their power-on configuration. See Section 7.1.

Неужто не заработает?